The present invention relates to translation look-aside buffers (TLB) for converting virtual addresses into physical addresses.
In a multiple user computer system, several different programs may want to use the same virtual address. In order to accomplish this, a translation look-aside buffer (TLB) contains a table which redirects the "virtual" address, which may be used by several programs, to a separate "physical" address for each program. This often occurs since each program prefers to start at address 0. A TLB can also be used when two different virtual addresses share the same physical address, and the system has to keep track of who wrote to that physical address last. A TLB can thus give the capability to control and track memory accesses. Some parts of memory can be designated as not writable or not readable by certain programs, for instance. In one version, the TLB distinguishes between the same virtual address for different programs using a process identification code (PID) associated with each program.
The TLB can be fully associative, direct-mapped or anywhere in-between. In a fully associative TLB, a particular translation can be anywhere in the TLB. Upon each memory access, the virtual address must be compared to all of the contents of the TLB. This would be very time consuming if done sequentially, and is thus done simultaneously through the use of a large amount of hardware and comparators. For a direct-mapped TLB, there is a single location in the TLB for the translation of each virtual page address. The virtual page address is thus used as an index to the proper location in the TLB for the translation. If the entry is not in the TLB, a trap to software is done. The software contains a full listing for all translations.
Although a processor may contain only a TLB and a main memory, a "cache" memory is often used in conjunction with a TLB. The cache memory is a small, quickly accessed memory which stores the most recently accessed data (or instructions) in anticipation of being used again and thus enabling the elimination of the longer access time to main memory. A cache memory will have a data portion and a tag portion. The tag portion contains the addresses of the data which are stored in the data portion. Each address requested by a program is compared with the tag addresses to see if the data is present. If it is present, the data is accessed from the data cache. Otherwise, the system has to go to main memory for the data. In that case, the data is used and is also stored in the cache so that it will be available for the next access. Typically, the data will be transferred from main memory to the cache, and then accessed from the cache. This way, only a single access path is required, since there is no need for a separate access directly to main memory bypassing the cache.
Data is typically written into a cache in a block, which includes the desired data and other bytes of data in the same area of memory. This is done because it is likely that a subsequent memory access will be to the same block.
A "fully associative" cache can hold as many blocks as will fit into the cache, independent of where the blocks were located in the main memory. However, on each memory access, all of the tags must be compared to the address, thus significantly slowing the memory access process or requiring more hardware. A less costly and faster cache system is a "direct-mapped" cache where each block has a designated in the cache. That location is used by a number of blocks. On a memory access, only that location needs to be accessed to determine if the tag for the desired block is present. This has the advantage of lower cost and greater speed, but the disadvantage that only one block from the group assigned to a single cache location can be present in the cache at any one time. The principal speed advantage of the direct-mapped structure is that the processor can start to use the data in parallel with a determination that it is the correct data (cache hit). If there is a cache miss, the use of the data is aborted.
The standard cache memory is a physical cache which takes a physical index and has physical tags (IBM 3090, DEC VAX 11/780, MIPS RC3260). A physical cache is located after the TLB has translated a virtual address into a physical address (see FIG. 5). This type of cache uses the address after it has been translated into a physical address by the TLB, and thus has a physical address for comparison to a physical cache tag. Another type of cache is a virtual cache which is indexed with a virtual address. A virtual cache eliminates the need for a TLB in the case of a cache hit, thus speeding up the memory access operation since the TLB translation does not need to be done before going to the cache. One type (Sun 3/200) stores a virtual address tag at a virtual address index (see FIG. 6). This type of virtual cache system requires system management to insure that virtual addresses which map to a single physical address are handled properly. Another type of virtual cache uses virtual indexes, but physical tags (ELXSI 6400). In this type, a TLB operates in parallel to generate the physical address for comparison to the cache tag to determine if there is a hit (see FIG. 7).